[NOSC] Verilog Implementations

[Eric Laforest <ecl@xxxxxxxxxxx>]

On Mon, Mar 26, 2001 at 09:36:59PM +0200, krejasi JR thus spake:
> Hi eric!
> 
> My attempt to do NOSC is by shematic and by CUPL when

Is there a free/cheap schematic capture program for DOS/Win/Unix
that can export to netlists or such so as to be suitable for
FPGA implementation?
(and capable of simulation would be a plus)

And what is CUPL?

> 
> BTW ,whats the mysterious problems?

You can go see at 
http://pet.dhs.org/~ecl/lswmfsc/

This is 5 implementations of a push-down stack with waveform dumps
(.vcd) and a PS image of the GTKWave output.

All 5 versions compile cleanly on Icarus Verilog, yet none of them
work right and I can't figure out why.

After 10+ tries, I'm seriously thinking of dropping HDLs altogether
and going back to schematics...besides, a good NOSC chip should
be simple enough so as to be manageable as a schematic. :)

Heck...I found out that there are well tested free VLSI design programs
from misc. Universities.  If I could get a dozen people together, then
creating a VLSI layout and getting it fabbed at MOSIS
(which tends to cost ~1000$US/mm^2 for a run of 0-25 chips)
would make more sense.

Eric LaForest

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