[NOSC] Verilog Implementations
- Subject: [NOSC] Verilog Implementations
- From: Eric Laforest <ecl@xxxxxxxxxxx>
- Date: Sun, 25 Mar 2001 16:00:32 -0500
Is there anyone out there who is doing 0-operand CPU design in Verilog?
I've seen several done in VHDL and a few done with schematics.
I'm currently attempting to do so, but am stumped by mysterious
problems.
Eric LaForest
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