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[NOSC] [colorforth] Color Forth for MISC (was:Hello, World! and other simple programs)

Forgive the cross-post, but this is more germane to the NOSC list.
Further replies should go there.

On Fri, Jul 27, 2001 at 05:49:17PM -0400, Jecel Assumpcao Jr thus spake:
> But I noticed that the people for whom I am doing this project have 
> more ambitious plans for the future, so I suggested that we might do 
> better with a MISC in FPGA instead. A 15K gate Spartan 2 costs $7, so 
> even with an external Flash memory it is half the price of the 
> ATmega103 we now have. A quick test of the free Xilinx tools with Dr. 
> Ting's nice P16 VHDL design resulted in a 25K layout running at a 
> surprising 50 MHz for the slowest speed grade chip. I am sure that a 
> design that used RAM for the stacks instead of individual flip flops 
> would be much smaller.

With the help of a couple of people I have a preliminary version of
a stack computer that is not unlike the F21 CPU core.

Machine Forth variant, Data/Address/Return stacks (16 deep each),
3 instructions/word, 32Kword codespace, 96Kw data space,
( both can be fetched/stored from/to)
...and it's 17 bits wide.
(3 5-bit instructions or a 15-bit address for 2-bit JMP/JMP0/CALL)
Memory and CPU run at same speed.
(couldn't figure out how to do the F21-style pre-fetch)
If last slot is not an I/O instruction, the next word
is prefetched then, else in next 'dummy' cycle.
All instructions and JMPs/CALLs/RETs are single-cycle.

It's coded in Verilog.
It synthesizes into ~15K gates (1100 LUTs or 1158 slices) on a
Virtex 50-E (XCV50E-6, the slowest speed grade).
Predicted speed is currently ~50MHz.

Things to be done:
(feedback is welcome)

Add interrupts (how many? 4?)
Add I/O lines (~37 enough? think of LCDs and IDE drives)
Clean up code for speed and size...and embarrasing mistakes. :)
Add serial EEPROM boot-loader (In-System-Programmable?)
Add some simple form of UARTs for interfacing to user and to
other identical systems.
(The Virtex II FPGAs have built-in differential signalling, which
would be a very nice feature for inter-system communications.)

The current idea is to mount the FPGA+SRAM+FPGA EEPROM+FORTH EEPROM
onto a single little board with the IO/IRQ/serial lines brought out
to a connector.  All peripheral interfacing is done through the
IO/IRQ lines to eliminate many of the headaches of interfacing
slow devices to a fast memory bus.
(At 50+MHz, most peripherals can't be used easily)
This goes with the idea that one board does only a few functions
at most if not only one (like behaving like an LCD or IDE
interface and controller) with only the bare minimum interfacing
hardware needed.

A larger system would be composed of several of these boards, each
running the core Forth and whatever code is needed to do its tasks.
(One for the LCD, one for the IDE drive, one for ethernet,
one for a few serial ports, one for sound, etc...)
The user gets his/her own board to act as interface.
All bords talk through some point-to-point or crossbar system.

Instead of designing one chip with intelligent co-processors like
the F21, I want to have as many peripheral functions implemented
in Forth on identical hardware.

This is just a quick overview of something I've been working on for
a while.  I would like feedback from the list members as there
is likely some really useful feature I've ommited or implemented
in a non-optimal way.  I try to keep it KISS unless it saves
on hardware and wiring or software speed/efficiency.

It's late and I must go sleep, hence please forgive the lack of
coherency if any. :)

Eric LaForest


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