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[Nosc] 25x thoughts

I have built some multicomputer machines, the largest one with 64 
nodes, and my first thought on reading about the 25x chip was "too 
little per node memory - how would you ever get something like Okad 
running on this thing?"

Well, after some reflection I came to the conclusion that this kind of 
speed requires a new way of thinking. It is possible to use repeated 
computation to eliminate memory. For example: when generating a 
reasonably high resolution image with a 60 MHz dot clock you can 
execute 1000 instructions (though it is only 40 per node) for each 
pixel you output. This means you can do it on the fly with no frame 
buffer at all. I have seen this called "wire speed processing" (see 

Our Von Neumann mentality was born in an age where we had to make every 
transistor count, and never waste any clock cycle. Perhaps the rules 
have changed?

Though $1 for such a chip seems like a dream, it could be even better. 
If a processor proved to be bad while testing, I would disable the 
whole row and column with that cpu and call the result the 16x chip. 
This would also work for multiple bad processors that are aligned 
horizontally or vertically. For two random bad cpus, we could have a 9x 
chip. Not throwing away those chips would have been a significant cost 
reduction in the 1980s, but I don't know what yields are like these 

It would be nice if all I/O pins on a side of the chip could be shared 
between all of the processors on that edge. Many interfaces require 
multiple pins and having to coordinate between more than one processor 
to achieve this would be a pain. All that would be needed would be a 
per cpu "direction register". When you read from the common input port 
address, you would see all of the pins and could mask just the ones you 
are interested in. When you write to the common output port address, 
only the bits you programmed as outputs would be affected.

Does anybody know any good 256Kx18 SRAM chips that *don't* cost around 
$40 each?

-- Jecel

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