Re: [colorforth] Realtek Ethernet driver

[Oninoshiko <oninoshiko@xxxxxxxxxxxxxxxxxxxx>]

On Sun, 6 Jun 2004, Mark Slicker wrote:

> The FIFO buffer is an intermediate step. Once a threshold is met the
> packet is transfered by the realtek card from the FIFO to host (main)
> memory. This operation is enabled by setting a bit in the Command
> Register on the realtek chip, and is independent of whether interupts are
> enabled either on the CPU or the realtek chip.

I stand corrected, on rereading, the buffer (main/host memory?) is a
cyclic buffer (8k+1536b overrun?). It looks like I have registers to
tell me where in this buffer I am (37h bit 0 (RX Buffer Empty), 38h-39h
(CAPR)). i wanted to conferm this.

> The interrupt is used for signaling. Chuck has enabled the ROK (Recieve
> OK) interupt, which will signal when a packet has succesfully been
> recieved to host memory.

am i understanding this correctly?

thanks for all your help,

Oninoshiko

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