No Subject
- To: MISC
- From: jfox@xxxxxxxxxx (Jeff Fox)
- Date: Wed, 16 Nov 1994 13:23:52 -0800
Date: 09 Sep 94 14:21:41 EDT
From: Chuck Moore <73662.1545@compuserve.com>
To: Jeff Fox <jfox@netcom.com>
Subject: F21
64 PADS A10 P7 P6 P5 Vdd Vss P4 P3 P2 P1
21 20 19 18 17 16 15 14 13 12
A11 22 11 P0
A12 23 10 RAM
Ao 24 9 8RAM
Ai 25 8 CAS
B 26 7 RAS
R 27 6 WE
G 28 5 A9
Vo 29 4 8
Vi 30 3 7
CLK 31 2 6
32 1 5
Vdd 33 64 4
Vss 34 63 3
So 35 62 2
Si 36 61 1
37 60 A0
D19 38 59 D0
18 39 58 1
17 40 57 2
16 41 56 3
15 42 55 4
14 43 54 5
44 45 46 47 48 49 50 51 52 53
13 12 11 10 Vdd Vss 9 8 7 6
PIN-OUT
64-Pin DIP: pins 1-64 same as pads 1-64
68-Pin PLCC: x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
25 x
26 8
27 7
28 6
29 5
30 4
31 3
32 2
33 1
34 64
35 63
36 62
37 61
38 60
39 59
40 58
x 57
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 x
PGA-65
Ai A12 A10 P6 Vdd P4 P3 P1 P0 SRAM 25 23 21 19 17 15 14 12 11 9
R Ao A11 P7 P5 Vss P2 FRAM CAS RAS 27 24 22 20 18 16 13 10 8 7
G B x WE A9 28 26 x 6 5
Vi Vo A8 A7 30 29 4 3
14M top A6 A5 31 32 2 1
Vdd Vss view A4 A3 33 34 64 63
So Si A1 A2 35 36 61 62
D19 D1 A0 37 38 58 60
D18 D17 D15 D12 Vdd D9 D7 D5 D3 D0 39 40 42 45 48 50 52 54 56 59
D16 D14 D13 D11 D10 Vss D8 D6 D4 D2 41 43 44 46 47 49 51 53 55 57
MEMORY
5 1Mx4 Page-mode DRAMs: Toshiba TC514400APL-80
3 8Kx8 15-ns SRAMs
1 8-bit PCMCIA card
INSTRUCTIONS
CPU - 200 to 300 Mips
00 jump 08 R@+ 10 COM 18 POP
01 IF 09 @+ 11 2* 19 A
02 call 0A # 12 2/ 1A DUP
03 -IF 0B @ 13 +* 1B SWAP
04 0C R!+ 14 -OR 1C PUSH
05 0D !+ 15 AND 1D A!
06 ; 0E 16 1E NOP
07 0F ! 17 + 1F DROP
I/O PORT
Write to pattern 1C1000: 0-7 data
10-17 direction: pattern 00000 input
3FC00 output
Read from 1C1000: 0-7 pad
8-9 0
10-17 direction
18-19 0
VIDEO
ANALOG
An 11-bit register is counted-down every CLK (14.32 MHz for NTSC).
It is reset from C at when it reaches 0. Thus it ticks at some
rate from 14 MHz to 7 KHz. C is to be loaded with a value for a
11-bit pseudo-random shift register (C0 = C10 -or C8).
A data word is read, then written to DRAM every tick. Bits 19-13
are sent to a binary 6-bit D-A converter. Current output is 0 - 100 mA.
The word is re-written with bits 5-0 from a 6-bit A-D converter. A
64-entry table look-up provides the corresponding binary value.
Conversions take 70 ns or so (depending on amplitude) over a range of
0 - 2.5 V. Thus signals up to 14 MHz can be handled. At high rates,
memory bandwidth is of concern.
Addresses do not increment beyond 10 bits. That is, 0FFFFF increments
to 0FFC00. Thus analog output cycles within a DRAM page.
If bit 10 is set the CPU is interrupted. At its next instruction
fetch a call to 000000 will be inserted. The interrupt is automatically
cleared.
The CPU sets the rate and 2 control bits in C. Bit 18 is on/off.
If bit 1 is set, the next address the CPU provides will be incremented
and latched into the address register. Thus the CPU must execute
the code
: ADDRESS ( a) 3BFFF p com a! nop
@ 2 # -or nop
! a! @ drop ;
with both ! and @ in the same word, to set the address. Bit 1 is
automatically reset, the other bits are undisturbed. The next analog
word will be the one after the address.
REGISTERS Bits
Address 21 0-20 DRAM only
Data 12
Buffer 13 0-5 input
6-9 0
10 interrupt
13-19 output
Clock 13 pattern 1C2000: 1 address from CPU
6-16 rate
18 on/off (0 at reset)
SERIAL
ADDRESSES
# pattern
000000 - 0FFFFF DRAM
180000 - 1BFFFF slow 8-bit RAM
1C0000 - 1FFFFF fast "
100000 - 101FFF slow RAM
140000 - 141FFF fast "
1C1000 I/O port
1C2000 analog clock
1C4000 serial clock
1E0000 configuration
bit 0 video on
18-19 8RAM page
POWER-UP
CPU Audio Video Serial
P 1AAAAA 0xxxxx 0AAAAA 0xxxxx
page 3 off off off
