a modified DRAM die with a MISC?

[Eugen Leitl <ui22204@xxxxxxxxxxxxxxxxxxxxxxx>]

Hiya co-MISCers,

excuse me if my basic assumptions are invalid, but
is there a basical (that means technical, not financial)
difficulty to integrate a MISC core, particularly a ultra-wide
data bus one as a integral part of (slightly modified)
standard DRAM die (e.g. a 1-4MBit one)?

The main advantage of such a beast would be: 

- drastically enhanced access speed (no need for the poor DRAM cell 
  straining its charge pump trying to pull a wire to logic high all the way 
  to the driver (and switching the driver)) - hence higher memory
  bandwidth

- extremely wide buses (up to 0.5-1 kBit, since there is no 
  bond pad/driver space constraint) - again, much higher memory bandwidth 

- low power consumption (no red-hot high-freq power drivers). 

- Moreover, if we use a wafer-local high-speed serial network 
  (e.g. hypergrid packet-switched one) wafer scale integration 
  (WSI) becomes feasible. No need for testing, cutting, packaging,
  etc., a major source of costs and new defects.

Am I talking sense? If not, why? If yes: I would like to
post (much) more on that subject. Any comments?

-- eugene