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[jfox@xxxxxxxxxx (Jeff Fox)]

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NETWORK 5/17/95

                     F21 SERIAL/NETWORK COPROCESSOR

F21 contains a serial/network coprocessor.  This coprocessor is turned
on and off by the CPU setting a bit in Cn the network configuration
register.  The serial/network coprocessor provides DMA and CPU interrupt
functions.  The configuration register contains a bit that when set causes
the unit to echo serial data from the input pin to the output pin with a
one bit delay.  The contents of two registers in the serial/network coprocessor
are compared to the contents of all data that passes through serial/network
coprocessor.  The Start of Message and End of Message registers are programmed
by the CPU to set the messages recognized by this particlar F21.  Whenever a
SOM pattern is seen the serial/network coprocessor begins a DMA tranfer to
or from memory using the address in the serial/network address register which
has previously been set by the CPU.  When an EOM pattern is seen in the
serial/network data the coprocessor stops a DMA transfer and interrupts
the CPU.

In normal operation there will be layers of network support software.  At
a low level a processor must act as network master and control the flow,
error correction, and housekeeping of the network.  The network master
will assign network SOM and EOM addresses on the network and control
which units are allowed to write at a given time.

A low level software network operation will be to mark a section of memory
for a DMA transfer, prepare the data, and queue up the request to send.
When the master gives this unit permission to send the message, the CPU
will set the serial/network coprocessor control bits to write rather than
read, and initiate a serial transmission that will interrupt the CPU of
both the sending and receiving units when it finishes.

In normal operation the serial/network coprocessor will be reading and
echoing serial data,  but it will not be making any memory access.
When it sees its own SOM it begins writing from the serial port to memory.
When it sees its own EOM it stops writing and interrupts the CPU.  The
CPU interrupt code will reset serial/network interrupt bit, process the
serial data for error control, and reset the serial/network coprocessor.
At a high level of network software control there will be words RX( and
G!.  RX( remotely executes a word by queueing up its execution vector
for a remote CPU interrupt somewhere on the network.  And G! queues up
a write to a location in the global memory, the distributed shared memory.
At the hardware levels these operations are supported by CPU interrupts
and DMA transfers across the network.

The serial/network coprocessor on the initial F21 prototypes will use
the same clock as the analog and video coprocessors.  A later version
may use a separate pin for network clock input.  There is an 11 bit
counter that counts down the timing from the input clock.  If a 14Mhz
xtal is being used to generate NTSC video timing for the video processor
this counter would provide a range from 14Mhz to 7Khz for the timing
of the bits on the serial/network coprocessor.  The upper limit for the
video clock on the initial F21 prototype is 20Mhz, and tests will be
made to see how fast the network interface can be clocked on F21.  The
internals of the serial/network coprocessor limit it to about 1Gbps,
so the network clock signal and network i/o signal quality will determine
the upper limit for serial/network operation.

                               REGISTERS

   The network interface is half-duplex: it can send or receive, but not
both at the same time.  Input and output pins are standard CMOS levels
(0-5 V, threshold at 2.5 V).  The coprocessor has 6 registers:

            Name  abbr  size  address_pattern  function
          Buffer          20   (internal)      Buffer memory
            Data          20   (internal)      Shift
         Address          21   (internal)      Address memory
   Configuration    Cn    20   1E8000          Specify configuration options
           Match   SOM    20   1E4000          Start Of Message pattern
           Match   EOM    20   1E2000          End Of Message pattern

Three of these registers can be read or written by the CPU by simply
accessing that location in memory.  The Buffer and Data registers are
internal only, and are not set or read by the CPU.  The CPU will also
set the Address register in the serial/network coprocessor by executing
a routine shown later that causes the serial/network coprocessor to
grab an address from the CPU and place it in this register.

Addressable registers have the following formats:

   bit 19 . . .  . . . .  . . . .  . . . .  . . . 0
   SOM  m m m m  g g g g  m m m m  m m m m  m m m m
   EOM  m m m m  m m m m  m m m m  m m m m  m m m m

    Cn  s o - -  c c c c  c c c c  c c c b  b a - x
        - 0 - -  - - - -  - - - -  - - - -  - - - -  power-up off

        m - bit must match
     gggg - needn't match if gggg = 0
        s - 1 send input onward             Normal operation
            0 sink input                    Master unit echos nothing
        o - 0 coprocessor off (power-up)
            1 coprocessor on
        x - 0 transmit, read memory         CPU sets this to send to network
            1 receive, write memory         Normal operation read from network
      c-c - clock rate                      count down timing clock
       bb - 0 20 bits/word                  only mode implemented on prototype
            1 16 (not implemented)
            2  8 (not implemented)
        a - address from Stack Processor    used by CPU to set address register


OPERATION

   An 11-bit register is shifted every CLK (14.32 MHz for NTSC).
It is reset from c-c when it reaches 0.  Thus it ticks at some
rate from 14 MHz to 7 KHz.  c-c is to be loaded with a value for a
11-bit pseudo-random shift register (b0 = b10 -or b8).

   Bits are shifted into the Data register every tick.  If receiving,
Data is transferred to Buffer every  bb  ticks and written to
memory.  If transmitting, Buffer is read from memory and transferred
to Data.

   If transmitting, the output pin is connected to Data bit 0.
If receiving onward (x is 1, s is 1), it's connected to bit 19.  This
passes the input through with a one-bit delay for re-clocking.
If receiving sinking (x is 1, s is 0), it's alternately connected to
bits 0 and 1 of EOM.

   There must be sufficient transitions in serial input to maintain
clock synchronization (TBD, probably every 5-10 bits).  The counter
is reset at every transition.  This synchronizes independent clocks
to within a tick (70 ns @ 14 MHz).  Bits are right-shifted into bit 20
and out of bit 0.

   Addresses do not increment beyond 10 bits.  That is, 0FFFFF increments
to 0FFC00.  Thus network I/O cycles within a DRAM page.

   Data is continuously compared with the Match registers.  If receiving,
when SOM is found, the length counter is reset (indicating a word align)
and data starts being recorded.  When EOM is found, the coprocessor is
halted (Cn18 reset) and the Stack processor interrupted.  EOM terminates
both received and transmitted messages.

   SOM has 8 bits intended to be a port address.  The 4 high-order bits
specify a group, and the 4 low-order bits a unit.  If the unit bits are
0, the data is recognized as broadcast to the entire group.  Examples:

   13800 - recognized only by unit 13800
   70AAA - recognized by units 71AAA - 7FAAA
   80000 - recognized by units 80000 - 8F000 (start bit)

SOM (and EOM) must be a pattern that will not occur within a message.
Since high-speed transmissions must have sufficient transitions to
maintain clock sync, an illegal string of 0s (or 1s) is one possibility.
Better is a reserved pattern that preserves sync.
If SOM is 80000 and EOM is 00000, the effect is of asynchronous start and
stop bits, though there must be 20 stop bits between messages.

   At power-up, the processor is off, registers undefined.  Setting sinking
receive will allow a message that sets a unique port address.  A future chip
might power-up with receive on and default SOM, EOM and Address.  This would
permit booting from the net.

   The Stack Processor sets the rate and control bits in Cn.  If Cn2 is
one, the next address the SP provides will be incremented and latched into
Address.  Thus the SP must execute the code

      : ADDRESS ( a)   17FFF p com a! nop
         @a 4 # -or nop
         !a a! @a drop ;

with both !a and @a in the same word, to set Address.  After the  @a  Cn2 is
automatically set to zero.  The next Network transfer will be will be at
the word after the SP address.

The pattern 17FFF when complemented makes the pattern 1E8000 which is the
address of the network configuration register Cn. Bit 4 the _a_ bit is
changed to force the serial/network coprocessor to prepare to latch the
next address used by the CPU.  The CPU then sets the CPU _a_ register
with the a! instruction and reads from that location in memory with
the @a instruction.  The !a and @a must be in the same word so that
the serial/network coprocessor will properly latch the address intended
for use as the network data transfer buffer.