Re: MuP21 Evaluation kit.

[rdr@xxxxxxxxxxxxx]

   Hi all,
	   I am thinking of purchasing the MuP21 eval board for a home
	   project, but before I commit the huge funding required :-)
	   I need some more info.

	   I want to add bit wise i/o, that is turn on/off relay, read
	   switch i/p etc.  Therefore I need to add some hardware, is
	   the board lyed out in a convenient fashion for this ?

The board has 8 bits output (a '574 latches the data) and 8 bits input
(a '245 places them on the bus when desired).  For address decoding in
the io address space, three bits of address are decoded by a '138
demultiplexor.  During io you have a 20 bit data bus, how much of that
you use is up to you.  If you need more than 6 io addresses you could
insert something in front of one of the select lines of '138...

	   Is there an "expansion connector" ?

There's a row of holes on one side of the board -- I think this is
supposed to allow you to connect up a pcmcia card in the address space
normally used by the eprom.  However, I don't see anything about it in
the docs I have open in front of me.

	   Would I build my i/o into the sram address space ?

I doubt it.

Here's a copy of my notes on the memory map.  [Note: these dual
address ranges are because there's two different ways of symbolizing
the electrical patterns on the bus.  Pattern is "active high", Numeric
is "even bits are active high, odd bits are active low."]

    Addresses Ranges		Interpretation (bit counts in decimal)
Numeric		Pattern
000000-0FFFFF	000000-0FFFFF	20 bit DRAM
100000-11FFFF	1A0000-1BFFFF	--
120000-13FFFF	180000-19FFFF	Slow 20 bit I/O (250 ns)
140000-		1E0000-		Configuration register
160000-17FFFF	1C0000-1DFFFF	Fast 20 bit I/O (50 ns)
180000-1BFFFF	100000-13FFFF	Slow 8 bit SRAM (250 ns)
1C0000-1FFFFF	140000-17FFFF   Fast 8 bit SRAM (50 ns)

There are 256K bytes of SRAM space, the high two bits of the address
bus are set by the top two bits of the configuration register (note:
these bits are inverted).  The low bit of the configuration register
enables the video coprocessor.  At boot the configuration register is
effectively set to C0000 (bank 0 of SRAM, video coprocessor off).

The MuP21 consumes 1 ma with video off, and approx 20.0 ma with video
on.

Note that pattern addresses aren't in numeric order.  For example, on
boot, instructions are fetched as follows

number  pattern
1AAAAA  100000
1AAAAB  100001
1AAAAC  100006
1AAAAD  100007
1AAAAE  100004
1AAAAF  100005

and an instruction fetch from address number 1AAAB0 would be from
pattern address 10001A.  This is of importance when programming an
eprom from a PC -- you need to remember to xor the addresses to
properly shuffle the data.

-- 
Raul D. Miller