MISC & F21

[Steve Atkins <atkinss@xxxxxxxxxxxxxx>]

Hi all,

  I've been lurking for a couple of months, following with
interest. I can't help feeling that I'm missing some background
though.

  Can anyone point me at some basic information about the misc
philosophy/goals etc. and maybe some of the implementations
that are being developed?

Cheers,
  Steve
--
-- Steve Atkins -- <atkinss@inmos.co.uk> -- +44 454 611439 --
     * Bug rate is measured per line of code.
     * VHDL and Verilog bug rate is about the same.
     * VHDL requires about 3X the number of lines of code to describe a
          given function as Verilog.