Re: P64 Math

[girling@xxxxxxxxx (Doug Girling)]

Regarding the adder width and carry propagate time:

At the risk of putting my foot squarely in it, has anyone considered
staggering the read/write signals across the word to keep abreast with the
carry?  (i.e., the read/write operation is skewed slightly with the least
significant byte/word being accessed one minor clock cycle before the next
most significant byte/word.)  It seems at first blush that this could
offer the simplicity of ripple carry hardware with little real performance
penalty because of the minor degree of pipelining it could allow.

Doug
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