Re: News on F21
- To: Eugene.Leitl@xxxxxxxxxxxxxxxxxxx
- Subject: Re: News on F21
- From: "Robert J. Brown" <rj@xxxxxxxxxxxxxx>
- Date: Mon, 10 Mar 1997 18:29:37 -0600
- CC: penev@xxxxxxx, MISC
- In-reply-to: <Pine.SOL.3.91.970310231726.12576S-100000@sun3> (message fromEugene Leitl on Mon, 10 Mar 1997 23:22:14 +0100 (MET))
>>>>> "Eugene" == Eugene Leitl <Eugene.Leitl@lrz.uni-muenchen.de> writes:
Eugene> An SRAM cell takes 4-6 transistors. Since unused silicon
Eugene> is oblivious to random defect hits but SRAM cells are not,
Eugene> yield will go down, and prices up.
Actually, on a recent project I was doing firmware for, I was told by
the hardware/Verilog guys that it only took 2 transistors to make an
SRAM cell, but they said that was comparing size, not actual
circuitry. Apparently, with SRAM being so regular in geometry, they
can make it more compact that random logic. So this would mean you
could get 2 to 3 times as many bits of SRAM as was mentioned in an
earlier post. This would run it up from about 4-6 KB to around 16 KB,
which is respectable for many applications, especially given Forth's
high code density.
--
-------- "And there came a writing to him from Elijah" [2Ch 21:12] --------
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Elijah Laboratories Inc.; 37 South Greenwood Avenue; Palatine, IL 60067-6328
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