on chip RAM

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

Some tentative figures have been given here for the amount of memory that could
be added in the 4 unused mm2 of the x21.
These figures were mainly based on a comparison with the stacks memory cells,
which occupy almost 80% of the active area of the chip (which is around 2 mm2)
for 32 words of 21 bits, so 4 mm2 were expected to add 64 more words.

These figures are very pessimistic, because RAM memory cells will not use as
much area as the stack memory cells.

Each stack memory cells is composed of 8 transistors:
- two complementary transistors for each of the two inverters
- two complementary pass transistors for each of the two bus connections
  (one "write=push" bus is driven by the S -resp. R- register to write it into
  the cell pointed to by the data -resp. return- stack pointer, and one
  "read=pop" bus is driven by the neighbour cell, also currently pointed to by
  the stack pointer, to read it into S -resp. R-)
These transistors, sized for fast register transfers, are bigger than the
smallest transistor allowed by the process.

The pitch of stack memory cells is fixed by the surrounding circuits:
- horizontally, the pitch is mainly determined by the ALU bit slice width
- vertically, the pitch is mainly determined by the drivers of the lines
  controlling the 4 pass transistors of the push/pop bus connections.

These pitch constraints do not need to be propagated to a RAM array.

The third metal layer, presently unused by Chuck, may lead to a denser layout.
Stackable vias, unavailable in the current .8 micron process, but available in
most smaller .5 and .35 processes, will save a lot of silicon area.
Denser layouts imply shorter wires, smaller impedances, and faster switching.

The transistors may be of minimal size, leading to slower access than with the
stacks, but much faster than with external memory, which must be routed through
the pads and the inter-chip wires, which altogether have an impedance orders of
magnitudes higher than the on-chip buses.

SRAM cells may be made even smaller, although slower, with fewer transistors
(6 or even 5) and only one read/write bus.
DRAM cells require a minimum of one transistor, but must be refreshed.

In both cases, memory cells may be organized in larger rows (4 or 8 words wide)
to factor the address decoder and drivers, and reduce the silicon area needed
for them, again at the price of slower access due to an added pass transistor.

Altogether, Chuck estimated that he should be able to add around 20 Kbits of
DRAM on-chip.  Even half of that would be great.  It still has to be done.

Christophe
--
email: Christophe.Lavarenne@inria.fr		tel: +33.1.39.63.55.80
INRIA, Domaine de Voluceau Rocquencourt		Institut National de Recherche
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