Re: MISC-d Digest V97 #13

[jfox@xxxxxxxx (Jeff Fox)]

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Dear MISC readers:

>From: Andrew Sieber <asieber@usa.net>
>Subject: Re: MISC video spec (640x480 ?)

>It seems to me you could generate any resolution you wanted if you were
>willing to sacrifice color.  If you use only black and white, you could
>run the external clock at more than 14.3MHz.  You'd then be generating
>only lumenance, but no chromanance signal, and since the lumenance does
>not have the 3.58MHz dependency, this should work.

True, except it isn't really just black/white, there is b/w and 13
shades of grey. 

Resolution will also more flexible with the RGB outputs on F21.

>Dave asked:

>Does anyone have a parts list for Tings MuP21*H* kit?
>
>Does it use DIP, SIMM, or zigzag DRAMs?
>
>What brands and speed of DRAMS have people had luck with on this kit?

The MuP21h board (the most recent one with the PLCC P21, uvprom, and serial i/o)
uses a 72pin SIMM just like the earlier kit (DIP P21, uvprom, and parallel i/o)
while the original development system (DIP P21, pcmcia ram card, 8255 parallel
i/o) used 5 1Mx4 dips.

A 1Mx32 72pin SIMM is used, 80ns or faster and most any brand should do
although when I put one on the second kit I had to cut of little plastic
pins on the SIMM because they were in places where there were no holes
in the board.  Things were designed for 80ns memory, but 70ns or 60ns
just gives you a little more margin for error and my 70ns Hitachis
let me crank up the voltage beyond 6 if I want.  I don't really know
if the 80ns Toshiba chips just don't run above 5.5v or if the P21 just
increases speed faster than they do and so are not fast enough above
that voltage.  I guess a scope or logic analyzer could reveal what it
is that fails with the 80ns Toshiba I have above 5.4v.

When I switched to Hitachi drams on the development system Chuck pointed
out that these Hitachi chips specified a higher refresh requirement than
the original Toshiba.  The video setup code in OK101F (available at my
web site and used with P21Forth) has a very small mod to put 4 refresh
instructions on each line of video coprocessor code instead of the 1
refresh instruction that was there.  I have run Dr. Ting's OK demos
however without problem on those Hitachi chips and it worked fine.
This tells me that these DRAM chips do work with the same amount of
refresh that was provided for the Toshiba chips because Dr. Ting has
the old 1 refresh per video line setup.   If you have a problem with
some particular brand of DRAM you might want to try 4 refresh per line
instead of 1.  It is a tiny modification.  Check the file OK16A.SEQ
and note the defs of BSR and HR.

\ 1/line or 525/33ms.  That's plenty for Toshiba, but the Hitachi
\ spec says 4 per line.  To do that change the video setup to:

': BSR  0. p dup !+      ( BBBB)
   05FF7. , BDEF7. , ;'  ( BSRS SSSS)
': HR  BSR BDFF7. p BDEF7. p ( SSRS SSSS)
   over over !+ !+ over over !+ !+ !+ !+
   9DEF7. , 00015. , ( KSSS BBBC)

\ ': BSR 0. p nop nop nop dup!!+ !!+  ( BBBB)
\    05FF7. , BDEF7. , ;'  (BSRS SSRS)

\ ': HR   BSR BDEF7. p nop nop nop dup!!+ !!+ ( SSRS)
\    BDEF7. p ( SSSS)
\    dup!!+ dup!!+ dup!!+ !!+
\    9DEF7. , 00015. , ( KSSS BBBC)

  AD6B5. p ( CCCC)
  dup!!+ dup!!+ !!+
  AD6A0. , ( CCCB)
  0. p ( BBBB)
  dup!!+ !!+ ;'

Anyway this was the mod to the video setup code from that version of OK.
As I say the old code actually seemed to work on the Hitachi chips anyway.

If you have a prolem with a particular brand of DRAM and your video 
setup code does not look like the above (commented out) version then
you might need to make a functionally equivalent change to make the
DRAM work properly with increased refresh.

Also Dr. Ting redesigned the video setup code sometime after the original
release of OK.  The original video code had the line framing instructions
in sequence with the pixel instructions on each line, this made each video
line 73h long.  A later version of the video setup has the start of line
framing instructions in a separate place from the pixel (and end of line)
instructions and made the separation between line 66h.  Dr. Ting did
this because he said it was easier to multply by 66H than 73H when
calculating pixel addresses.  I had suggested making it 80H because it
is definately faster to multiply by 80H than 66H or 73H.  We are currently
using an offset of 80h between video lines on the video code at iTV.
One of the issues of More on Forth Engines has the video code with lots
of comments explaining what the video setup code is really doing for
those interested in the details of the video setup code.

Jeff 

+-----------------------------------------------------+
|   Jeff Fox                                          |
|   jfox@dnai.com              Ultra Technology Inc.  |
|   jeff@itvcorp.com           the iTV Corporation    |
|   http://www.dnai.com/~jfox/                        |
+-----------------------------------------------------+