F21c

[Penio Penev <penev@xxxxxxx>]

Hi MISC-ers,

I don't know whether any of you have noticed, but Jeff has updated his F21
page -- http://www.dnai.com/~jfox/f21.html

There we read:  Today F21c was submitted to Mosis for fabrication.

Congratulations!

We hope that everything goes well and all of us can order chips at some
time in the near future :-) 

[ As I typed this, Jeff made the announcemet to MISC.  Anyway, I still
have a few questions :-]

I have some questions:

ROM:  

- How much ROM is there on-chip?  

- How much ROM can be there on-chip?

- What about SRAM?

- We see that the setup time is  8ns, and the access time is 4ns.  What
makes the setup time so big?  Can it be shaved off?


Timings:

- 40ns access + 10ns setup for DRAM is 50ns = 20MHZ , which is 80 MIPS. 
On the other hand, it is stated, that it can execute at 100 MIPS from DRAM. 
Is there a controversy?  Does the "20% fast" timing have anything to do
with this, and if yes, what DRAMs are needed? 

- 12ns + 10 ns = 22ns = 45 MHZ = 180 MIPS, versus 200 claimed.

--
Penio Penev <Penev@pisa.Rockefeller.edu> 1-212-327-7423