Memories are made of....

[wmor1@xxxxxxxxxxxxxxxxxxxxx]

> Date sent:      Tue, 19 Aug 1997 09:17:55 -0700 (PDT)
> From:           jfox@dnai.com (Jeff Fox)
> To:             MISC
> Subject:        interview with Chuck

> Dear MISC Readers:
> 
> >From: "Michael A. Losh" <mlosh@tir.com>
> >Subject: Questions for a Chuck Moore interview
> 
> I have planned to ask Chuck a half dozen questions about Forth,
> his ideas about hardware/software etc and give him about five
> minutes to talk about each one.


> Chuck has already said in published interviews that memory on chip is
> terribly expensive for everyone and that other chip designers add very
> expensive memory when then add it to a processor.  (ie, more than half
> of the silicon on that $3000 micro is on chip memory.)
> 
> P21 has the equivalent of ten cells of memory on chip and they take
> up about 75% of the area that Chuck has layed out.  This is a very
> long ways away from integrating large amounts of memory on chip.
> 

I think the solution (short term) has come up many times.  People 
have said that one reason memory takes so long is because of the 
time to power up the I/O pads.  If we could eliminate this need and 
use shorter paths betweeen the two (so the story went) we would have 
higher speeds (if we can find said die).  There are chips appearing 
on the market that intergrate 2 chips in a microcontroller, ram, 
eeprom, etc.  Those multiple device surface mount packages could be 
usefull, boring signals to the other side of an insulating substrate 
could allow two devices, one on eah side.  I have been 
hereing of announcements in the electronic design press fora 
few years of processes that are as cheap to implement as the 
seperate devices.  I even have seen them stacked vertically 
and horizontally together.   But more realistic to get some 
simple set up in one page would be the way to go.  Because we only 
need maxium speed for the stacks we could effectivelly use dies 
that meet the instruction load requirements of /4 the max mip 
rating.  This could merely be a working prototype for future 
OEM customers to order batches of.  At least you maybe able to wave 
the big performance figure around.


> 
> >Are there too few layers to lay out the memory
> >cells effectively?
> 
> Without a lot of explanation this is a pretty meaningless question.
> Memories can be made with any number of layers and in any process.
> Of course in order to make the best memories and processors these
> are not the same processes.  Modern memories are made with more
> layers to provide "vertical transistor layers" in DRAMs that
> I have not seen used in processor design. 

Yes this is curiouse, I had an simple idea for a external hard storage 
(which didn't work) but I would be restricted down to one layer, is 
that possible?

> 
> My idea was not to try to get Chuck to explain the technical details
> of VLSI design, sub-micron, quantum-design, process variations 
> available etc.  
> 
> The idea of this interview is Forth.  It is clear to me that Chuck's
> idea of Forth is very different than the ideas that most Forth user's
> have about Forth.

OK, first question, Forth is a dieing language to the computer 
community, how can we meet there needs (hardware independence, 
reliabilty, componentism etc) and beat them at their game?  So 
basically to take it beyond them but keeping performance, efficency 
etc, something they do very badly.
 
> keyboards, Java, C++, Visual Basic, program editors, web browsers,
Yes Java, what does he think?

Wayne. 
------------------------------------------------------------------------
Wayne Morellini  <wmor1@student.monash.edu.au>

Post Graduate Student Representative.
Rusden Campus, Deakin University, Vic, Australia.

GradDip Media Studies (Current), Bach InfoTech (Distinction)
& AD Business(Computing).
------------------------------------------------------------------------