Re: MISC-d Digest V98 #28 (fwd)

[Rick Hohensee <humbubba@xxxxxxxxxxxxxx>]

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> Subject: Re: MISC-d Digest V98 #28
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> On Fri, 17 Jul 1998, GARY B. LAWRENCE wrote:
> 
> |      I would like to get some feedback from this group on a subject that
> | interests me at the moment. I would like to see F21's be used in a 
> | multiprocessor version of a multitasking operating system. 
> 
MISC makes feasible what I call "DMA-tasking". This is not parallel,
but is I believe where MISC can assert itself very visibly. 
One CPU is the scheduler, and provides other general services perhaps. The scheduler
has it's own bus, and a "bus" of MISCs. A task switch is a CPU switch.
0-latency task switching. The bus-of-miscs can be on one chip, run cool,
and need maybe 10 more pins for 128 MISCs. 

Tricks might be possible where 2 miscs operate in echelon on the same
memory to give a larger effective machine state, but the latency thing
will sell it for general multi-media use.

Rick Hohensee  

Rick Hohensee          http://cqi.com/~humbubba
cLIeNUX   xart   kandinski  cycluphonics   ratioles  H3sm   Md., USA