clockless logic

[David Cary <d.cary@xxxxxxxx>]

I'm looking for information of "clockless logic".
"clockless logic", "self-timed logic" can be used in standard FPGAs.
Because it doesn't need clocks, it promises to reduce power consumption.

Unfortunately,
"the /metastable state/ is the bane of asynchronous digital systems."
A good explanation of the (surprising) problems this causes
in asynchronous circuits (and why it is not a problem in clocked circuits)
is in the book _Computation Structures_ by Ward and Halstead (section 4.6).

Most people seem to be going to synchronous (clocked) logic.
Is this because difficulties of asynchronous logic are really so large that
once you've worked around them, the net performance of a circuit is no
better than a clocked-logic equivalent ?

Or is this merely because it's *so* much easier to properly design
synchronous logic than it is to properly design clockless logic ?

One application of clockless logic is
  the New Media Processor (NMP) chip
  http://techweb.cmp.com/eet/news/96/929news/clock.html
  from Sharp Corp.
  "Sharp plans to market the chip in high volume at "much cheaper than
$50," Tanatsugu said."

  Clockless Logic
  http://www.sanders.com/hpc/CL/

  clockless logic
  http://www.ionet.net/~caryd_osu/david/html/vlsi.html#clockless

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+ David Cary "mailto:d.cary@ieee.org"; "http://www.rdrop.com/~cary/";
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