F21/P21 "improvements"?

["Mark Bottomley" <markb@xxxxxxxxxxx>]

	I have looked at the instruction set for the F21 and found that for a class
of problems relating to vectors, it is not clear to me how to easily handle
3 memory addresses for doing X op Y -> Z.  The A and R registers can perform
as two of the address registers.  I propose (at the expense of using some of
the unused opcodes in the base 32) that a second address register B that is
logically stacked below A, but which has access to memory might be useful.
The additional instructions would be @B+ and !B+.  The A instruction would
be modified to push the current value of A into B and pop T into A.  The A!
instruction would be modified to push the current value of A into T and pop
B into A with B remaining unchanged.  I don't claim to fully understand the
architecture and I may be missing something.  I also understand that adding
something to a "Minimal" instruction set seems odd.  I hope this isn't an
old idea from before I started monitoring this list.

	Mark...

	Mark Bottomley
	mailto:markb@zucotto.com
	Zucotto Systems Inc.
	Ottawa, Ontario, Canada