Misc 34

["Wayne Morellini" <waynemm@xxxxxxxxxxx>]

Dear Jeff

About that optical cpu stuff Chuck is being approached with.  I read about 
new magnetic
processors and memory technology a number of months ago promising 40,000 
more efficency.
An artical I have implies that Cambridge University's Department of 
engineering have working
prototypes (Dr Russell Cowburn and Dr mark Welland) at room temperature 
(procces can fit
upto 5.5 Million transistors allready).  I was going to look it up to see if 
it was true or not and
email you, but I forgot.  The other atrical (that I can't find) said that 
magnetic chips would run
really fast (I think 10's of Ghz) with memory on chip at the same speed as 
the processor, and
memory array technology replacing Hard disk storage (but most of the 
technologies in this
artical aren't viable yet).  But the Cambridge group has something working.  
It is probably much
more doable/affordable than the optical systems and maybe Cambridge would 
like to try a Misc
chip with onchip memory.

I have also heard that the latest silicon on insulator processes (and other 
new techniques) use low
k values.  Does this raise the theorectically speed limit of Chuck's designs 
which were limited
by capacitance effects?

>It basically comes down to a deal with a company that is making memory 
>chips
>to drop a MISC CPU down on the die with connections to on chip memory.  The
>idea is very attractive since you can make chips that are small and need
>few pins.  The memory is faster than off-chip memory.  The only small
>problem is that it requires a company that is making memory chips that
>wants to do this.  It has been very close before but the Asian economy went
>through some rather large bumps a few years ago.
Pity.  What about some of these:

  A) Something that is not very pie in the sky that has been done before: 
Controller chip
  shipped in the same package as a memory die (vertically mounted but could 
be
  horizontally mounted).  Because the tracks between the two chips can be so 
small the memory
  could be run faster (less capactiance and buffering), with no extra pins 
in a small package.  So
  you get fast memory without the extra expense.  Apart from this chip 
stacking techniques could
  reduce the track length, or surface mounting (both more costly I've been 
told here).  It could
  even be used to implement an simple (old design) ultra small cache system.

  B) Why not implement a page (or more) of fast ram on chip (with logically 
seperate bus for
  dual access ;) to run routines?  It is an embedded processor so it doesn't 
really matter that it's
  not cache.  You would get 90% of the benefits for 10% of the cost of 
cache.

  C) I have just been reading about the latest DDR sdram announcements.  
Lower capacitance
  (does that help with your speed problem?), lower power consumption, lower 
latency ;) and
  higher speed than PC133 SDRAM.

  D) IBM Last year announced a process to insert memory in the processor and 
pack it more
  densely.  Upto 100% faster, 25% denser, 50% + less power.  It is hard to 
tell if these are the
  actual projected figures, as the article quotes seperate figures for IBM's 
silicon on insulator and
  copper processes.

Jeff who was working on that p21 project you mentioned, with all the extra 
interfacing?

>As far as I know three people have made P21 boards, perhaps more.
>... Penio

There's a name I haven't heard for a while what happened to Penio?

Thanks.

Wayne.
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