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I agree that having multiple MISC chips running
routines in Parallel would make a great computer. But MISC can be even
more powerful using Parallelism on the instruction set.
Regardless of how little I actually know about
processors, hardware, software, and my lack of experience in any field - I'm
slowly trying to design a 64 bit version of the 21. Influenced by Vector
Parallel Processing, I propose packing four 16 bit words into a 64 bit
cell. A single instruction would process all 4 values. I'm thinking
that the instruction set might have to be extended to 6 bit instructions to
accomodate both the 16 bit and 64 bit instructions. Why would I want to do
this? 16 bit would be good for sound, video, characters (unicode, ebcdic),
integers, and such.
Not quite "minimal", but I feel that since the 21
instructions are already the simplest and most used logic, the chances of ADD
occuring more than once within a given time frame is great, so why not use that
as an advantage. Cache just stores instructions recently used, because
there is a great chance those routines will be used again. But why let
hardware guess when a programmer, or at the least an optomizing compiler, can
arrange data ahead of time?
A 64 bit VPMISC processor, using 6 bit
instructions, would be able to process 40 colors, samples, characters, or
integers within a single fetch. And 64 bit data would be used for memory
addressing, database management, etc., and high precision fixed point
integers. And all this while keeping it zero operand. Now network 16
of those together in parallel...
Too bad I wouldn't be able to get the funding for
such a processor...
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