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[NOSC] Verilog Implementations

> > chip should
> > be simple enough so as to be manageable as a
> > schematic. :)
> That is what i have found out too! :-)
> Actually, wich development software beeing used for
> the NOSC design, VERILOG,VHDL,CUPL or plain
> schematic
> is "not" the problem i think. The problem i find is
> to find a compiler/assembler, floor planner for the
> binary design file!

Actually, what i wanted to say is its not a problem,
at least its not a big one, since the NOSC is simple
to implement regarding to the SW tool in question.

But it is a problem allso. Most tools has very high
learning curves and if one does VLSI there is loots
of things to say about SPICE if used! 

Actually i wished everything was following the KISS
concept. Remove the last S for the non offending


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