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RE: F21/P21 "improvements" | memory cost


Dear MISC readers:

Alan wrote:
>You mention that "With old slow DRAM only 140mips max, well below the
>500 in the CPU.  In faster SRAM it goes up to 250.  With a faster memory
>interface good code could keep close to the 500."  If most, if not all
>of the code of the program on-chip, wouldn't the memory interface run at
>the full 500?  The only off-chip memory accesses would be for additional
>data that could be loaded a full memory page at a time, taking advantage
>of page-mode access.  Wouldn't this be the most efficient method of
>utilizing memory space?

It is fast.  In production it is relatively cheap.  I have mentioned
prototyping issue of paying $100 per word.  But F21c did have some on-
chip memory althought it was ROM.  But yes, with fast on-chip memory
you can run at faster speeds.  efficent isn't clearly defined here.
If it means if you spend N times as much up front your chip will be
Z times faster then ok.  If it means efficient use of resources it
would mean switching to a smaller chip (8 bits instead of 20 maybe
to get on chip memory) or some other tradeoff unless someone is
offering to pay the difference the issue is budget management.

>I know that you have made certain choices in your work based on what was
>available to you.  I am asking my questions so that I may learn about
>what is possible and what trade-offs will need to be made.  Whether I
>will be able to implement the ideas may be a different story, but only
>time will tell.  You have real-world experience with this topic, so you
>are the most qualified person I know to ask.  Is cost the only
>consideration for placing the CPU and memory on the same chip?  You
>mentioned that they are usually made with different processes, but you
>alluded to the option of designing a CPU to take advantage of memory
>processes.  Would doing so affect the stability of the processor, or
>limit the types of circuits that could be used in the processor design?

Not that I know of.

Jeff Fox