[ColorForth] port e1

["Chuck Moore" <chipchuck@xxxxxxxxxxxxxx>]

Mark Slicker reports that ports eb and ed cause bus delays, as (I think)
does e1. So this 'feature' varies amongst platforms. Doubtless there is a
principle known to a few BIOS writers and hardware designers. If only we
knew it.

There used to be books (I have The Undocumented PC) that revealed such
secrets. They seem to have gone out of fashion.

I note that such a bus delay is more than an idle loop. It probably keeps
address/data present on the bus, for compatiblity with older, slower
peripherals. But why do current superIO chips need it?

And I've seen e1 provide an enormous delay (us).
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