Re: F21 specs
Jeff Fox:
ARCHITECTURE
...
A register (T) acts as the top of the data stack. All data are placed
in T; its prior contents are pushed onto S.
The ALU acts upon T and S, leaves its result in T and pops S for
binary operations (+ -or and).
A register (A) is used to address data.
A program counter (P) is used to address instructions.
The return stack stores subroutine return addresses (and occassional data).
A configuration register (C) specifies timing and addressing options.
Apparently C has an address but none of the other registers do?
Jeff Fox:
The configuration register stores patterns; the package pins
display patterns.
This seems to imply that the other coprocessors (video, analog,
serial) use numbers rather than patterns?
Jeff Fox:
INSTRUCTIONS
...
The 27 instruction codes are:
00 else unconditional jump 08 @R+ fetch, address in R, increment R
01 T=0 jump if T0-19 zero 09 @A+ fetch, address in A, increment A
...
Are instruction bits pattern bits or numeric bits? I presume that for
the case of addressing they're [inverted] numeric bits.
Jeff Fox:
macros
A! @A @
A! !A !
dup dup -or com -1
dup dup -or 0
over com and -or OR
A! push A@ pop SWAP
# (com) push ; long_jump
When an opcode appears in slots 1-3, it must be complemented. An
add instruction must be coded nop + if carry needs to propagate
only 10 places, or nop nop + for a full 20 places. This is not
required in slot 0 if the instruction fetch provides equivalent
delay.
I think it would be really handy to have a cnop macro -- this would
insert a nop only for slot2..slot4 instructions. one cnop would
typically provide for 10 bits of carry, two cnops would provide for 20
bits of carry. Finally, 3 cnops would guarantee the next
instruction occurs in slot 1.
Jeff Fox:
INTERRUPT
An interrupt can occur when an instruction word is fetched. The
requested instruction is replaced by a 15-bit call to 00000 in home page.
The current address will be pushed onto R when the call is executed.
At least 3 stack positions must be available (reserved) for interrupts,
2 on data and 1 on return. Register A must be saved and restored.
The cause of the interrupt is in C2-0. C must be read to determine it.
The interrupt is cleared when C is rewritten, which may only occur once.
The source of the interrupt is cleared by the corresponding address bit
in the address of C. It is intended that this code be executed at the
end of interrupt processing (say for C0):
A 015554 # com ( pattern 1 1110 0000 0000 0000 0--1) A!
@A !A A! ;
The address bits A2-0 specify the interrupt(s) to be cleared. @A !A A! ;
must all be in the same word. Another interrupt may occur immediately.
This isn't completely clear -- what are the stack positions needed
for? I presume this termination restores A? Or is A trashed? What's
going on here?
Also, how are interrupt causes encoded? I see more than three
potential interrupt sources -- perhaps some causes have priority over
other causes? I suppose that a robust interrupt service routine would
need to deal with all potential interrupt causes?
Jeff Fox:
SPEED
4 instructions are obtained with each fetch. Each instruction
is executed in 3 ns, for a peak rate of 330 Mips. Sustained rate
depends upon the number of memory-access instructions. With no
data memory accesses but with instruction memory setup and access:
RAM DRAM
12 15 25 40 140 ns
270 220 140 90 30 Mips
I presume that for 15ns or faster RAM you need to do nop nop + to get
complete carry propagation even if the stack was last modified by a
slot 4 instruction?
Jeff Fox:
MEMORY
CONFIGURATION
Typical: 0-5 DRAMs, 0-3 SRAMs, 1 ROM
5 1Mx4 Page-mode DRAMs: Toshiba TC514400APL-80
or 1 1Mx16 and 1 1Mx4 :
and/or 3 8Kx8 SRAMs :
1 8-bit PCMCIA card :
or 1 8-bit ROM :
Er.. does this mean the F21 is viable with only ROM and no DRAM or
SRAM? If so, what's performance like? [I didn't see any mention of
an on-chip SRAM page.]
Jeff Fox:
ADDRESS MAP 1995 DATA
address = pattern
000000 - 0FFFFF DRAM 20 bit 1 M words (or 256K words)
180000 - 1BFFFF slow 8 bit SRAM 1 M bytes as 4 256k pages
1C0000 - 1FFFFF fast 8 bit SRAM 1 M bytes as 4 256k pages
100000 - 101FFF slow 20 bit SRAM 8 K words
140000 - 141FFF fast 20 bit SRAM 8 K words
16BAAA 1C1000 I/O port register
168AAA 1C2000 analog clock register
16EAAA 1C4000 network clock register
162AAA 1C8000 network match register
14AAAA 1E0000 configuration register
Any docs on the network clock and network match registers? Presumably
the network clock is functionally similar to the analog clock
register? Presumably the network match register has something to do
with different serial formats (e.g. synchronous vs asynchronous
serial, ethernet, ...)? Or perhaps it's for output (as opposed to
input)? Or perhaps it's for somehow adapting to an otherwise unknown
input speed? Perhaps the network interface writes out whatever data
is in memory just before it reads stuff in? I think this area needs
more doc.
Jeff Fox:
I/O PORT
Write to pattern 1C1000: 0-7 data
10-17 direction: pattern 00000 input
3FC00 output
Read from 1C1000: 0-7 pad
8-9 0
10-17 direction
18-19 0
(The production F21 will provide for external interrupt on the I/O port.)
Presumably data written to the i/o port is latched while reads are
unlatched (except of course that the data is placed on the stack)?
Jeff Fox:
VIDEO 1995 SPECS
... The pixel clock can run up to 20 MHz, with a corresponding
frame rate.
Presumably the pixel clock is controlled by the crystal. Why only
20MHz? Bus limitations? Logic complexity?
Puzzledly,
--
Raul Miller
