Re: P64 Math
On Fri, 11 Aug 1995, Mike Losh wrote:
> I'm
> curious whether 64 bit-wide math would require some different approaches in
> terms of silicon. Specifically, the carry propogation of the P21 limits how
> fast a program can perform successive additions or multiply steps.
(for large-precision numbers)
> F21 will
> have similar constraints from what I've seen. Will the planned P32 use an adder
> with ripple carry? Is there a limit to how wide it is reasonable to use such an
> adder? Maybe 32 and 64 bit designs will require the much more complex carry
> prediction silicon in order to get acceptable performance.
As I understand it, the push to wider busses is to alleviate the _memory_
bottleneck problem, which will drive "peak advertised MIPs" up to (SRAM
cycles/sec)*[(bus width)/5].
On the other hand, one shouldn't change their data types. If I need/care
about 6 bits do describe a quantity in a solution to my problem, why would
the change to a faster processor change my representation to 32 or 64
bits?
I would rather have some fast bit-field packing/unpacking instructions
rather than carry prediction, which most probably I will never (with
probability measure close to zero) need.
--
Penio Penev <Penev@venezia.Rockefeller.edu> 1-212-327-7423
