Re: presentation for SVFIG
- To: <misc>, "Tor Silfverberg" <d97tsi@xxxxxxxxxx>
- Subject: Re: presentation for SVFIG
- From: "vic plichota" <atsvap@xxxxxxxxxxx>
- Date: Fri, 31 Mar 2000 06:35:38 -0500
- References: <200003311045.MAA07410@kobra.efd.lth.se>
> I dont know anything about SDRAM interfaces
It's a fucking nightmare -- optimal use req's that the CPU provide
advance notice of it's burst / pipeline / L1-cache expectations, and
a highly-buffered bus interface.
cheers - vic.
