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Forth Processor in VHDL-FP1


I posted the VHDL code for a Forth Processor created in VHDL for FPGA's, etc.  Here is the deal.  You may use all or part of the code in your own processors if you share your enhancements for only the Forth Processor Core Design with the MISC list and myself.
 
This goal of this processor design is KISS (Keep it Simple Stupid).  If the Forth Processor core takes up less than 50% of the FPGA in your design, then you can have concurrent processes for those other functions you need great speed for.  Remember, the most exciting thing about using VHDL to create custom FPGA's is they are really you are creating parallel processors on a single chip.  I think a super fast Forth core which can execute multiple instructions per cycle is really not necessary for most applications.  The Forth Processor will allow programming capabilities and off load low speed processes that don't need speed.  This will allow us to use smaller and cheaper FPGA's and give field programming as well.
 
I think Forth could get its crown back as the embedded system language of choice this way.  
 
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