F21 questions

[rdr@xxxxxxxxxxxxx (Raul Miller)]

[This is a resend of some follow-up questions I sent to Jeff Fox.
Jeff originally sent a response back to just Jeff (and pointed out
that though the message looked like it was intended for misc it never
got there).  Anyways, Jeff's already seen these but most of the rest
of you haven't.  At the bottom is Jeff's further responses to the
questions I posed here.  Note that I've editted out a couple comments
that have to do with this "who's this being sent to" stuff, and
replaced them with this note.  I hope this isn't too confusing...]

what I sent to Jeff:
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   Raul Miller:
      >Apparently C has an address but none of the other registers do?

   Jeff Fox:
      The coprocessor clock and control registers have addresses as does
      the memory processor and cpu configuration register.  Presumably if
      the coprocessors are not being used certain bits could be read and
      written in those registers as a scratch pad.  But you would have to
      be careful or you would turn on a coprocessor.

   Good point.  [However, I meant that the contents of the data stack,
   return stack and A never have any addresses.]

   Raul Miller:
      >I think it would be really handy to have a cnop macro -- this would
      >insert a nop only for slot2..slot4 instructions.  one cnop would
      >typically provide for 10 bits of carry, two cnops would provide for 20
      >bits of carry.  Finally, 3 cnops would guarantee the next
      >instruction occurs in slot 1.

   Jeff Fox:
      macros will be easy to add either to a macro assembler or to an
      optimizing native code compiler.  The problem I see with
      calculating the timing is more complex on F21 because of all the
      bits in the configuration register to control the cpu and memory
      access speeds.

   Yes, this is why I suggested cnop rather than smart + (the programmer
   needs to choose between cnop and nop).

   Jeff Fox:
      Yes, exactly, if you are not adding small numbers or ORING two
      parts of a whole.  You can for instance use + to OR two numbers
      if there is no carry involved.  FFC00 003FF +    needs no nops

   If there's no carry it's probably better to use -or.

   -or is + before doing ripple carry.
   and is the initial seed for ripple carry.

   Raul Miller:
      >Presumably data written to the i/o port is latched while reads are
      >unlatched (except of course that the data is placed on the stack)?

   Jeff Fox:
      What is problem with the stack?  You can say set 4 bits for input
      and 4 bits for output, and write a pattern for output where you
      output bits are latched, then read and see what is on the unlatched
      input bits.  Why is the stack a problem?

   Not a problem -- I was just trying to be precise.

   Raul Miller:
      >Presumably the pixel clock is controlled by the crystal.  Why only
      >20MHz?  Bus limitations?  Logic complexity?

   Note that faster dot clocks would let a person compose various video
   formats such as for multi-sync monitors.

   -- 
   Raul Miller


how Jeff replied:
----------------------------------------------------------------------
   Return-Path: <jfox@netcom.com>
   Date: Wed, 10 May 1995 21:36:52 -0700
   From: jfox@netcom.com (Jeff Fox)
   To: rdr@legislate.com

   Dear Raul,

   >Good point.  [However, I meant that the contents of the data stack,
   >return stack and A never have any addresses.]

   No no addresses for A or stacks or PC

   >Note that faster dot clocks would let a person compose various video
   >formats such as for multi-sync monitors.

   Sure, we will have to see what the upper limit is.  The first
   prototype will only have one clock.  This will be used by all three
   i/o coprocessors each with their own multiply up or count down
   timing registers.  We may go with 3 separate input clocks on the
   final device.  It would be one of the easier changes, though I
   don't think it is one Chuck favors.  We will see.  I would like
   to run the network and video off of separate clocks I think,
   we will see how well then run.
   The internal logic on the network will run up to about 1G, but
   how fast i/o can actually go in and out of the chip is something
   else.  Also without a multiply up you couldn't use a 1G xtal
   for the clock into network anyway.  We will see what the
   maximum clock rates will be.

   Jeff Fox 

----------------------------------------------------------------------

Finally, I mailed him back and talked a bit about using a single clock
with several big counters, and workarounds for the speed problem with
ripple carry.  [I didn't save a copy of that letter, so I can't quote
it verbatim.]

Raul D. Miller