P16 In FPGA: Video Working!
- To: MISC
- Subject: P16 In FPGA: Video Working!
- From: Dave Lowry <lowry@xxxxxxxxxxxxxxxxx>
- Date: Wed, 31 Mar 1999 19:11:54 -0600 (CST)
The video arbitration logic is now working. The CPU/pixel clock is
8 MHz (limited by EPROM speed), which gives a 320x350 monochrome
picture.
The CPU runs at 6 FIPS (Forth Instructions Per Second). It's not
8 because every 4th slot goes to instruction fetch. The video
does a fetch every 16th slot.
There's also a 1 bit i/o port which is used for bit-banged serial,
currently at 115,200 baud.
With video and 5 deep parameter and return stacks, 3/4 of a Xilinx
4010 is being used. The remainder will probably go to bigger stacks.
More later.
-Dave
